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authorcinap_lenrek <cinap_lenrek@felloff.net>2019-07-25 13:55:17 +0200
committercinap_lenrek <cinap_lenrek@felloff.net>2019-07-25 13:55:17 +0200
commit1717368f640180cab63a870a19d650276172cbfd (patch)
tree33476f5afc21613248a054e644a59656d369a4cf /sys/src/9/bcm/dma.c
parent706926f8184456e44dd509eb057e59884907b1ec (diff)
bcm, bcm64: clean dma destination buffer before issuing dma in case of non cache-line-size aligned buffer
Diffstat (limited to 'sys/src/9/bcm/dma.c')
-rw-r--r--sys/src/9/bcm/dma.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/sys/src/9/bcm/dma.c b/sys/src/9/bcm/dma.c
index 81b68199f..07b067259 100644
--- a/sys/src/9/bcm/dma.c
+++ b/sys/src/9/bcm/dma.c
@@ -174,6 +174,7 @@ dmastart(int chan, int dev, int dir, void *src, void *dst, int len)
switch(dir){
case DmaD2M:
ctlr->flush = dst;
+ dmaflush(1, dst, len);
ti = Srcdreq | Destinc;
cb->sourcead = dmaioaddr(src);
cb->destad = dmaaddr(dst);
@@ -187,6 +188,7 @@ dmastart(int chan, int dev, int dir, void *src, void *dst, int len)
break;
case DmaM2M:
ctlr->flush = dst;
+ dmaflush(1, dst, len);
dmaflush(1, src, len);
ti = Srcinc | Destinc;
cb->sourcead = dmaaddr(src);