diff options
| author | cinap_lenrek <cinap_lenrek@felloff.net> | 2019-08-19 16:42:20 +0200 |
|---|---|---|
| committer | cinap_lenrek <cinap_lenrek@felloff.net> | 2019-08-19 16:42:20 +0200 |
| commit | 6280c0f17bf3919cf6c2506fec6edfa0a7ec10fe (patch) | |
| tree | 54c78088d5a59d59e19082ce5f31c849292545ba /sys/src/9/bcm64/clock.c | |
| parent | a611fe20e16318b4b61dc52b4f71e59ccbc203d5 (diff) | |
bcm64: do not use OTP_BOOTMODE_REG to determine OSC frequency (thanks richard miller)
the register does not seem to be accessible on the Rpi 3b.
so instead hardcode oscfreq in the Soc structure.
Diffstat (limited to 'sys/src/9/bcm64/clock.c')
| -rw-r--r-- | sys/src/9/bcm64/clock.c | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/sys/src/9/bcm64/clock.c b/sys/src/9/bcm64/clock.c index f24fedb93..f7b3e55f7 100644 --- a/sys/src/9/bcm64/clock.c +++ b/sys/src/9/bcm64/clock.c @@ -121,23 +121,15 @@ clockinit(void) syswr(CNTP_TVAL_EL0, ~0UL); if(m->machno == 0){ - int oscfreq; - syswr(CNTP_CTL_EL0, Imask); *(u32int*)(ARMLOCAL + GPUirqroute) = 0; - /* bit 1 from OTP bootmode register determines OSC frequency */ - if(*((u32int*)(VIRTIO+0x20f000)) & (1<<1)) - oscfreq = 19200000; - else - oscfreq = 54000000; - /* input clock to OSC */ *(u32int*)(ARMLOCAL + Localctl) = 0; /* divide by (2^31/Prescaler) */ - *(u32int*)(ARMLOCAL + Prescaler) = (((uvlong)SystimerFreq<<31)/oscfreq)&~1UL; + *(u32int*)(ARMLOCAL + Prescaler) = (((uvlong)SystimerFreq<<31)/soc.oscfreq)&~1UL; } else { syswr(CNTP_CTL_EL0, Enable); intrenable(IRQcntpns, localclockintr, nil, BUSUNKNOWN, "clock"); |