diff options
| author | cinap_lenrek <cinap_lenrek@felloff.net> | 2019-08-26 22:34:38 +0200 |
|---|---|---|
| committer | cinap_lenrek <cinap_lenrek@felloff.net> | 2019-08-26 22:34:38 +0200 |
| commit | 128ea44a89c7905612ad2fa5a61a9325ddfb5e1e (patch) | |
| tree | c8d115acc86fb2e50e38af952741b725bd4366ae /sys/src/9/bcm64 | |
| parent | 91a8d03040a3533e27f51d33bbbfed33d84b5043 (diff) | |
kernel: expose no execute bit to portable mmu code as SG_NOEXEC / PTENOEXEC, add PTECACHED bits
a portable SG_NOEXEC segment attribute was added to allow
non-executable (physical) segments. which will set the
PTENOEXEC bits for putmmu().
in the future, this can be used to make non-executable
stack / bss segments.
the SG_DEVICE attribute was added to distinguish between
mmio regions and uncached memory. only matterns on arm64.
on arm, theres the issue that PTEUNCACHED would have
no bits set when using the hardware bit definitions.
this is the reason bcm, kw, teg2 and omap kernels use
arteficial PTE constants. on zynq, the XN bit was used
as a hack to give PTEUNCACHED a non-zero value and when
the bit is clear then cache attributes where added to
the pte.
to fix this, PTECACHED constant was added.
the portable mmu code in fault.c will now explicitely set
PTECACHED bits for cached memory and PTEUNCACHED for
uncached memory. that way the hardware bit definitions
can be used everywhere.
Diffstat (limited to 'sys/src/9/bcm64')
| -rw-r--r-- | sys/src/9/bcm64/mem.h | 6 | ||||
| -rw-r--r-- | sys/src/9/bcm64/mmu.c | 3 |
2 files changed, 6 insertions, 3 deletions
diff --git a/sys/src/9/bcm64/mem.h b/sys/src/9/bcm64/mem.h index ba8bef451..450dba012 100644 --- a/sys/src/9/bcm64/mem.h +++ b/sys/src/9/bcm64/mem.h @@ -124,10 +124,12 @@ #define PTEUSER PTEAP(1) #define PTEWRITE PTEAP(0) #define PTERONLY PTEAP(2) +#define PTENOEXEC (PTEPXN|PTEUXN) +#define PTECACHED PTEMA(MA_MEM_WB) #define PTEWT PTEMA(MA_MEM_WT) -#define PTEUNCACHED PTEMA(MA_MEM_UC) -#define PTEDEVICE PTEMA(MA_DEV_nGnRE) +#define PTEUNCACHED PTEMA(MA_MEM_UC) +#define PTEDEVICE PTEMA(MA_DEV_nGnRE) /* * Physical machine information from here on. diff --git a/sys/src/9/bcm64/mmu.c b/sys/src/9/bcm64/mmu.c index 2fbe19747..ca8186322 100644 --- a/sys/src/9/bcm64/mmu.c +++ b/sys/src/9/bcm64/mmu.c @@ -453,7 +453,8 @@ putmmu(uintptr va, uintptr pa, Page *pg) flushasidvall((uvlong)up->asid<<48 | va>>12); else flushasidva((uvlong)up->asid<<48 | va>>12); - *pte = pa | PTEPAGE | PTEUSER | PTEPXN | PTENG | PTEAF | PTESH(SHARE_INNER); + *pte = pa | PTEPAGE | PTEUSER | PTEPXN | PTENG | PTEAF | + (((pa & PTEMA(7)) == PTECACHED)? PTESH(SHARE_INNER): PTESH(SHARE_OUTER)); if(pg->txtflush & (1UL<<m->machno)){ /* pio() sets PG_TXTFLUSH whenever a text pg has been written */ cachedwbinvse(kmap(pg), BY2PG); |