diff options
| author | cinap_lenrek <cinap_lenrek@felloff.net> | 2019-08-26 22:34:38 +0200 |
|---|---|---|
| committer | cinap_lenrek <cinap_lenrek@felloff.net> | 2019-08-26 22:34:38 +0200 |
| commit | 128ea44a89c7905612ad2fa5a61a9325ddfb5e1e (patch) | |
| tree | c8d115acc86fb2e50e38af952741b725bd4366ae /sys/src/9/bcm | |
| parent | 91a8d03040a3533e27f51d33bbbfed33d84b5043 (diff) | |
kernel: expose no execute bit to portable mmu code as SG_NOEXEC / PTENOEXEC, add PTECACHED bits
a portable SG_NOEXEC segment attribute was added to allow
non-executable (physical) segments. which will set the
PTENOEXEC bits for putmmu().
in the future, this can be used to make non-executable
stack / bss segments.
the SG_DEVICE attribute was added to distinguish between
mmio regions and uncached memory. only matterns on arm64.
on arm, theres the issue that PTEUNCACHED would have
no bits set when using the hardware bit definitions.
this is the reason bcm, kw, teg2 and omap kernels use
arteficial PTE constants. on zynq, the XN bit was used
as a hack to give PTEUNCACHED a non-zero value and when
the bit is clear then cache attributes where added to
the pte.
to fix this, PTECACHED constant was added.
the portable mmu code in fault.c will now explicitely set
PTECACHED bits for cached memory and PTEUNCACHED for
uncached memory. that way the hardware bit definitions
can be used everywhere.
Diffstat (limited to 'sys/src/9/bcm')
| -rw-r--r-- | sys/src/9/bcm/arm.h | 1 | ||||
| -rw-r--r-- | sys/src/9/bcm/gpio.c | 2 | ||||
| -rw-r--r-- | sys/src/9/bcm/mem.h | 4 | ||||
| -rw-r--r-- | sys/src/9/bcm/mmu.c | 2 |
4 files changed, 7 insertions, 2 deletions
diff --git a/sys/src/9/bcm/arm.h b/sys/src/9/bcm/arm.h index 45f47f2ab..cc032cccd 100644 --- a/sys/src/9/bcm/arm.h +++ b/sys/src/9/bcm/arm.h @@ -293,6 +293,7 @@ #define L1noexec (1<<4) #define L2wralloc (1<<6) /* L2 TEX (small pages) */ #define L2sharable (1<<10) +#define L2noexec (1<<0) /* L2 XN (small pages) */ /* attributes for memory containing locks -- differs between armv6 and armv7 */ //#define L1ptedramattrs (Cached | Buffered | L1wralloc | L1sharable) diff --git a/sys/src/9/bcm/gpio.c b/sys/src/9/bcm/gpio.c index 0e4ddcb0c..d05295c1b 100644 --- a/sys/src/9/bcm/gpio.c +++ b/sys/src/9/bcm/gpio.c @@ -130,7 +130,7 @@ gpiomeminit(void) Physseg seg; memset(&seg, 0, sizeof seg); - seg.attr = SG_PHYSICAL; + seg.attr = SG_PHYSICAL | SG_DEVICE | SG_NOEXEC; seg.name = "gpio"; seg.pa = (GPIOREGS - soc.virtio) + soc.physio; seg.size = BY2PG; diff --git a/sys/src/9/bcm/mem.h b/sys/src/9/bcm/mem.h index 6471e9b83..5d0b9a1c5 100644 --- a/sys/src/9/bcm/mem.h +++ b/sys/src/9/bcm/mem.h @@ -79,13 +79,15 @@ #define PPN(x) ((x)&~(BY2PG-1)) /* + * These bits are completely artificial. * With a little work these move to port. */ #define PTEVALID (1<<0) #define PTERONLY 0 #define PTEWRITE (1<<1) +#define PTECACHED 0 #define PTEUNCACHED (1<<2) -#define PTEKERNEL (1<<3) +#define PTENOEXEC (1<<4) /* * Physical machine information from here on. diff --git a/sys/src/9/bcm/mmu.c b/sys/src/9/bcm/mmu.c index 851cb6c5e..7de489456 100644 --- a/sys/src/9/bcm/mmu.c +++ b/sys/src/9/bcm/mmu.c @@ -255,6 +255,8 @@ putmmu(uintptr va, uintptr pa, Page* page) x |= L2AP(Urw); else x |= L2AP(Uro); + if(pa & PTENOEXEC) + x |= L2noexec; pte[L2X(va)] = PPN(pa)|x; cachedwbtlb(&pte[L2X(va)], sizeof(PTE)); |