diff options
| author | cinap_lenrek <cinap_lenrek@felloff.net> | 2019-05-19 16:54:50 +0200 |
|---|---|---|
| committer | cinap_lenrek <cinap_lenrek@felloff.net> | 2019-05-19 16:54:50 +0200 |
| commit | c881e33e8ed668f4d5a2102c113e3edb1ea80d44 (patch) | |
| tree | 225ede9ebd28a718a1dada66d451fa1a73731992 /sys/src/9/bcm | |
| parent | d667607c26626219d8dfc1871f0a4d8ef92c240e (diff) | |
bcm, bcm64: fix cache operations for dma and emmc
always clean AND invalidate caches before dma read,
never just invalidate as the buffer might not be
aligned to cache lines...
we have to invalidate caches again *AFTER* the dma
read has completed. the processor can bring in data
speculatively into the cache while the dma in in
flight.
Diffstat (limited to 'sys/src/9/bcm')
| -rw-r--r-- | sys/src/9/bcm/dma.c | 4 | ||||
| -rw-r--r-- | sys/src/9/bcm/emmc.c | 2 |
2 files changed, 4 insertions, 2 deletions
diff --git a/sys/src/9/bcm/dma.c b/sys/src/9/bcm/dma.c index 84c7f0c73..e0d073ae1 100644 --- a/sys/src/9/bcm/dma.c +++ b/sys/src/9/bcm/dma.c @@ -170,7 +170,7 @@ dmastart(int chan, int dev, int dir, void *src, void *dst, int len) ti = 0; switch(dir){ case DmaD2M: - cachedinvse(dst, len); + cachedwbinvse(dst, len); ti = Srcdreq | Destinc; cb->sourcead = dmaioaddr(src); cb->destad = dmaaddr(dst); @@ -183,7 +183,7 @@ dmastart(int chan, int dev, int dir, void *src, void *dst, int len) break; case DmaM2M: cachedwbse(src, len); - cachedinvse(dst, len); + cachedwbinvse(dst, len); ti = Srcinc | Destinc; cb->sourcead = dmaaddr(src); cb->destad = dmaaddr(dst); diff --git a/sys/src/9/bcm/emmc.c b/sys/src/9/bcm/emmc.c index 53efe4325..d1906de06 100644 --- a/sys/src/9/bcm/emmc.c +++ b/sys/src/9/bcm/emmc.c @@ -398,6 +398,8 @@ emmcio(int write, uchar *buf, int len) } if(i) WR(Interrupt, i); + if(!write) + cachedinvse(buf, len); poperror(); okay(0); } |