diff options
| author | Sigrid Solveig Haflínudóttir <sigrid@ftrv.se> | 2022-08-15 23:42:15 +0000 |
|---|---|---|
| committer | Sigrid Solveig Haflínudóttir <sigrid@ftrv.se> | 2022-08-15 23:42:15 +0000 |
| commit | 7fd7d627e565b624e9cc1fecd837deb82f035d33 (patch) | |
| tree | 9fc4c90af42f09a86fac7403285138a838428fa4 /sys/src/9/imx8 | |
| parent | 423b54a0aeea198c8d4c0cbb23a17236d68910ec (diff) | |
imx8: enable/expose tmu
Diffstat (limited to 'sys/src/9/imx8')
| -rw-r--r-- | sys/src/9/imx8/ccm.c | 2 | ||||
| -rw-r--r-- | sys/src/9/imx8/main.c | 15 |
2 files changed, 17 insertions, 0 deletions
diff --git a/sys/src/9/imx8/ccm.c b/sys/src/9/imx8/ccm.c index ec83b5fb5..f0a529fcc 100644 --- a/sys/src/9/imx8/ccm.c +++ b/sys/src/9/imx8/ccm.c @@ -760,6 +760,8 @@ static Clock clocks[] = { { "pcie_mem.mstr_axi_clk", MAIN_AXI_CLK_ROOT, 37 }, { "pcie_mem.slv_axi_clk", MAIN_AXI_CLK_ROOT, 37 }, + { "tmu.clk", IPG_CLK_ROOT, 98 }, + { "pcie2_clk_rst.auxclk", PCIE2_AUX_CLK_ROOT, 100 }, { "pcie2_clk_rst.mstr_axi_clk", MAIN_AXI_CLK_ROOT, 100 }, { "pcie2_clk_rst.slv_axi_clk", MAIN_AXI_CLK_ROOT, 100 }, diff --git a/sys/src/9/imx8/main.c b/sys/src/9/imx8/main.c index 324feb5c8..17dce7651 100644 --- a/sys/src/9/imx8/main.c +++ b/sys/src/9/imx8/main.c @@ -251,6 +251,20 @@ cpuidprint(void) iprint("cpu%d: %dMHz ARM Cortex A53\n", m->machno, m->cpumhz); } +static void +tmuinit(void) +{ + Physseg seg; + + setclkgate("tmu.clk", 1); + memset(&seg, 0, sizeof(seg)); + seg.attr = SG_PHYSICAL | SG_DEVICE | SG_NOEXEC; + seg.name = "tmu"; + seg.pa = VIRTIO + 0x260000 - KZERO; + seg.size = BY2PG; + addphysseg(&seg); +} + void main(void) { @@ -289,6 +303,7 @@ main(void) links(); chandevreset(); lcdinit(); + tmuinit(); userinit(); mpinit(); mmu0clear((uintptr*)L1); |