diff options
author | cinap_lenrek <cinap_lenrek@felloff.net> | 2015-02-07 02:52:23 +0100 |
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committer | cinap_lenrek <cinap_lenrek@felloff.net> | 2015-02-07 02:52:23 +0100 |
commit | b8cf3cb879a19c001796329ebe266104d13e63be (patch) | |
tree | 745534899e603d5336347c846ad286c3535c43fc /sys/src/9/omap/mmu.c | |
parent | f215b660b30cc5e5d318922f545441b4ac14b200 (diff) |
kernel: reduce Page structure size by changing Page.cachectl[]
there are no kernels currently that do page coloring,
so the only use of cachectl[] is flushing the icache
(on arm and ppc).
on pc64, cachectl consumes 32 bytes in each page resulting
in over 200 megabytes of overhead for 32gb of ram with 4K
pages.
this change removes cachectl[] and adds txtflush ulong
that is set to ~0 by pio() to instruct putmmu() to flush
the icache.
Diffstat (limited to 'sys/src/9/omap/mmu.c')
-rw-r--r-- | sys/src/9/omap/mmu.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/sys/src/9/omap/mmu.c b/sys/src/9/omap/mmu.c index 05b4dc38c..f54359ff6 100644 --- a/sys/src/9/omap/mmu.c +++ b/sys/src/9/omap/mmu.c @@ -330,10 +330,9 @@ putmmu(uintptr va, uintptr pa, Page* page) * rather than direct mapped. */ cachedwbinv(); - if(page->cachectl[0] == PG_TXTFLUSH){ - /* pio() sets PG_TXTFLUSH whenever a text pg has been written */ + if(page->txtflush){ cacheiinv(); - page->cachectl[0] = PG_NOFLUSH; + page->txtflush = 0; } //print("putmmu %#p %#p %#p\n", va, pa, PPN(pa)|x); } |