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authorcinap_lenrek <cinap_lenrek@felloff.net>2021-01-17 11:55:39 +0100
committercinap_lenrek <cinap_lenrek@felloff.net>2021-01-17 11:55:39 +0100
commit999e98b9b856ae4fc75b3ad33783488e33cdd426 (patch)
treec33439781b7342456c41b7f8982e3e26174f7efd /sys/src/9/omap/usbehciomap.c
parent3240008dd182a0d88fb2d0d5ffc5e88accdd957f (diff)
usbehci: use 64-bit base address, remove resetlck, simplify scanpci()
Diffstat (limited to 'sys/src/9/omap/usbehciomap.c')
-rw-r--r--sys/src/9/omap/usbehciomap.c18
1 files changed, 8 insertions, 10 deletions
diff --git a/sys/src/9/omap/usbehciomap.c b/sys/src/9/omap/usbehciomap.c
index 8be97c323..e9db47f86 100644
--- a/sys/src/9/omap/usbehciomap.c
+++ b/sys/src/9/omap/usbehciomap.c
@@ -40,17 +40,15 @@ ehcireset(Ctlr *ctlr)
opio->seg = 0;
}
- if(ehcidebugcapio != ctlr->capio){
- opio->cmd |= Chcreset; /* controller reset */
- coherence();
- for(i = 0; i < 100; i++){
- if((opio->cmd & Chcreset) == 0)
- break;
- delay(1);
- }
- if(i == 100)
- print("ehci %#p controller reset timed out\n", ctlr->capio);
+ opio->cmd |= Chcreset; /* controller reset */
+ coherence();
+ for(i = 0; i < 100; i++){
+ if((opio->cmd & Chcreset) == 0)
+ break;
+ delay(1);
}
+ if(i == 100)
+ print("ehci %#p controller reset timed out\n", ctlr->capio);
/* requesting more interrupts per µframe may miss interrupts */
opio->cmd |= 0x10000; /* 1 intr. per ms */