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authorcinap_lenrek <cinap_lenrek@felloff.net>2020-09-13 20:33:17 +0200
committercinap_lenrek <cinap_lenrek@felloff.net>2020-09-13 20:33:17 +0200
commit4f85115526a87063489dc7cf347343bd520159b1 (patch)
treef9666d5c85ba6153f35dd50c672e1750ecdd9805 /sys/src/9/ppc
parentd7b541eaf317ca3586bf18a6a189dabae81d1e21 (diff)
kernel: massive pci code rewrite
The new pci code is moved to port/pci.[hc] and shared by all ports. Each port has its own PCI controller implementation, providing the pcicfgrw*() functions for low level pci config space access. The locking for pcicfgrw*() is now done by the caller (only port/pci.c). Device drivers now need to include "../port/pci.h" in addition to "io.h". The new code now checks bridge windows and membars, while enumerating the bus, giving the pc driver a chance to re-assign them. This is needed because some UEFI implementations fail to assign the bars for some devices, so we need to do it outselfs. (See pcireservemem()). While working on this, it was discovered that the pci code assimed the smallest I/O bar size is 16 (pcibarsize()), which is wrong. I/O bars can be as small as 4 bytes. Bit 1 in an I/O bar is also reserved and should be masked off, making the port mask: port = bar & ~3;
Diffstat (limited to 'sys/src/9/ppc')
-rw-r--r--sys/src/9/ppc/fns.h6
1 files changed, 0 insertions, 6 deletions
diff --git a/sys/src/9/ppc/fns.h b/sys/src/9/ppc/fns.h
index 5ae2f8097..0606e3b69 100644
--- a/sys/src/9/ppc/fns.h
+++ b/sys/src/9/ppc/fns.h
@@ -67,12 +67,6 @@ void mmuinit(void);
void mmusweep(void*);
int newmmupid(void);
void outb(int, int);
-int pcicfgr16(Pcidev*, int);
-int pcicfgr32(Pcidev*, int);
-int pcicfgr8(Pcidev*, int);
-void pcicfgw16(Pcidev*, int, int);
-void pcicfgw32(Pcidev*, int, int);
-void pcicfgw8(Pcidev*, int, int);
void procsave(Proc*);
void procsetup(Proc*);
void procfork(Proc*);