diff options
| author | cinap_lenrek <cinap_lenrek@felloff.net> | 2022-07-30 12:44:43 +0000 |
|---|---|---|
| committer | cinap_lenrek <cinap_lenrek@felloff.net> | 2022-07-30 12:44:43 +0000 |
| commit | 7a225e5331749e1c656661f7c1c5cc2767aa13d8 (patch) | |
| tree | c473cbd4e384f59e1e431160a30291936b23dcc2 /sys/src | |
| parent | 438f5e951fecbdac38e36f7a01ed31c78b14320e (diff) | |
imx8: increase cpu frequency from 1.4 to 1.6ghz
the RM seems to be outdated in this regard, saying
the core is targeted at 1.4ghz.
Diffstat (limited to 'sys/src')
| -rw-r--r-- | sys/src/9/imx8/ccm.c | 5 | ||||
| -rw-r--r-- | sys/src/9/imx8/clock.c | 2 |
2 files changed, 4 insertions, 3 deletions
diff --git a/sys/src/9/imx8/ccm.c b/sys/src/9/imx8/ccm.c index 036d1e3e9..ec83b5fb5 100644 --- a/sys/src/9/imx8/ccm.c +++ b/sys/src/9/imx8/ccm.c @@ -146,7 +146,7 @@ enum { }; static int input_clk_freq[] = { - [ARM_PLL_CLK] 1400*Mhz, + [ARM_PLL_CLK] 1600*Mhz, [GPU_PLL_CLK] 1600*Mhz, [VPU_PLL_CLK] 800*Mhz, [DRAM_PLL1_CLK] 800*Mhz, @@ -1015,7 +1015,8 @@ Found: && ((reg[1] ^ cfg1) & ~(1<<31)) == 0) return; - reg[0] |= 1<<14; /* bypass */ + /* bypass */ + reg[0] |= 1<<14; reg[1] = cfg1; diff --git a/sys/src/9/imx8/clock.c b/sys/src/9/imx8/clock.c index 5148176e7..6789ab8c5 100644 --- a/sys/src/9/imx8/clock.c +++ b/sys/src/9/imx8/clock.c @@ -46,7 +46,7 @@ clockinit(void) /* TURBO! */ setclkrate("ccm_arm_a53_clk_root", "osc_25m_ref_clk", 25*Mhz); - setclkrate("ccm_arm_a53_clk_root", "arm_pll_clk", 1400*Mhz); + setclkrate("ccm_arm_a53_clk_root", "arm_pll_clk", 1600*Mhz); } tstart = sysrd(CNTPCT_EL0); do{ |