diff options
author | Sigrid Solveig Haflínudóttir <sigrid@ftrv.se> | 2023-05-10 20:57:17 +0000 |
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committer | Sigrid Solveig Haflínudóttir <sigrid@ftrv.se> | 2023-05-10 20:57:17 +0000 |
commit | eaf799e8c4e25df6953046544ec5ef5e36fc921a (patch) | |
tree | fd28fa72da0cd390b10581fff65f14df6b46de8e /sys/src | |
parent | 6723fdf7b7c7fc3231bb1868139c768301ff03b9 (diff) |
libmach/acid: add basic FP support for arm64
Diffstat (limited to 'sys/src')
-rw-r--r-- | sys/src/libmach/7.c | 78 | ||||
-rw-r--r-- | sys/src/libmach/7db.c | 19 |
2 files changed, 92 insertions, 5 deletions
diff --git a/sys/src/libmach/7.c b/sys/src/libmach/7.c index 4d176ffe3..72ef535e6 100644 --- a/sys/src/libmach/7.c +++ b/sys/src/libmach/7.c @@ -8,13 +8,16 @@ #include "/arm64/include/ureg.h" +#define REGSIZE sizeof(struct Ureg) +#define FPREGSIZE 520 + #define REGOFF(x) (uintptr)(&((struct Ureg *) 0)->x) +#define FP_REG(x) (REGSIZE+16*(x)) +#define FP_CTL(x) (FP_REG(32)+4*(x)) #define SP REGOFF(sp) #define PC REGOFF(pc) -#define REGSIZE sizeof(struct Ureg) - Reglist arm64reglist[] = { {"TYPE", REGOFF(type), RINT|RRDONLY, 'Y'}, @@ -52,6 +55,75 @@ Reglist arm64reglist[] = {"R2", REGOFF(r2), RINT, 'Y'}, {"R1", REGOFF(r1), RINT, 'Y'}, {"R0", REGOFF(r0), RINT, 'Y'}, + + {"FPSR", FP_CTL(1), RINT, 'X'}, + {"FPCR", FP_CTL(0), RINT, 'X'}, + + {"F31", FP_REG(31), RFLT, 'F'}, /* double */ + {"F30", FP_REG(30), RFLT, 'F'}, + {"F29", FP_REG(29), RFLT, 'F'}, + {"F28", FP_REG(28), RFLT, 'F'}, + {"F27", FP_REG(27), RFLT, 'F'}, + {"F26", FP_REG(26), RFLT, 'F'}, + {"F25", FP_REG(25), RFLT, 'F'}, + {"F24", FP_REG(24), RFLT, 'F'}, + {"F23", FP_REG(23), RFLT, 'F'}, + {"F22", FP_REG(22), RFLT, 'F'}, + {"F21", FP_REG(21), RFLT, 'F'}, + {"F20", FP_REG(20), RFLT, 'F'}, + {"F19", FP_REG(19), RFLT, 'F'}, + {"F18", FP_REG(18), RFLT, 'F'}, + {"F17", FP_REG(17), RFLT, 'F'}, + {"F16", FP_REG(16), RFLT, 'F'}, + {"F15", FP_REG(15), RFLT, 'F'}, + {"F14", FP_REG(14), RFLT, 'F'}, + {"F13", FP_REG(13), RFLT, 'F'}, + {"F12", FP_REG(12), RFLT, 'F'}, + {"F11", FP_REG(11), RFLT, 'F'}, + {"F10", FP_REG(10), RFLT, 'F'}, + {"F9", FP_REG(9), RFLT, 'F'}, + {"F8", FP_REG(8), RFLT, 'F'}, + {"F7", FP_REG(7), RFLT, 'F'}, + {"F6", FP_REG(6), RFLT, 'F'}, + {"F5", FP_REG(5), RFLT, 'F'}, + {"F4", FP_REG(4), RFLT, 'F'}, + {"F3", FP_REG(3), RFLT, 'F'}, + {"F2", FP_REG(2), RFLT, 'F'}, + {"F1", FP_REG(1), RFLT, 'F'}, + {"F0", FP_REG(0), RFLT, 'F'}, + + {"f31", FP_REG(31), RFLT, 'f'}, /* double */ + {"f30", FP_REG(30), RFLT, 'f'}, + {"f29", FP_REG(29), RFLT, 'f'}, + {"f28", FP_REG(28), RFLT, 'f'}, + {"f27", FP_REG(27), RFLT, 'f'}, + {"f26", FP_REG(26), RFLT, 'f'}, + {"f25", FP_REG(25), RFLT, 'f'}, + {"f24", FP_REG(24), RFLT, 'f'}, + {"f23", FP_REG(23), RFLT, 'f'}, + {"f22", FP_REG(22), RFLT, 'f'}, + {"f21", FP_REG(21), RFLT, 'f'}, + {"f20", FP_REG(20), RFLT, 'f'}, + {"f19", FP_REG(19), RFLT, 'f'}, + {"f18", FP_REG(18), RFLT, 'f'}, + {"f17", FP_REG(17), RFLT, 'f'}, + {"f16", FP_REG(16), RFLT, 'f'}, + {"f15", FP_REG(15), RFLT, 'f'}, + {"f14", FP_REG(14), RFLT, 'f'}, + {"f13", FP_REG(13), RFLT, 'f'}, + {"f12", FP_REG(12), RFLT, 'f'}, + {"f11", FP_REG(11), RFLT, 'f'}, + {"f10", FP_REG(10), RFLT, 'f'}, + {"f9", FP_REG(9), RFLT, 'f'}, + {"f8", FP_REG(8), RFLT, 'f'}, + {"f7", FP_REG(7), RFLT, 'f'}, + {"f6", FP_REG(6), RFLT, 'f'}, + {"f5", FP_REG(5), RFLT, 'f'}, + {"f4", FP_REG(4), RFLT, 'f'}, + {"f3", FP_REG(3), RFLT, 'f'}, + {"f2", FP_REG(2), RFLT, 'f'}, + {"f1", FP_REG(1), RFLT, 'f'}, + {"f0", FP_REG(0), RFLT, 'f'}, { 0 } }; @@ -62,7 +134,7 @@ Mach marm64 = MARM64, /* machine type */ arm64reglist, /* register set */ REGSIZE, /* register set size */ - 0, /* fp register set size */ + FPREGSIZE, /* fp register set size */ "PC", /* name of PC */ "SP", /* name of SP */ "R30", /* name of link register */ diff --git a/sys/src/libmach/7db.c b/sys/src/libmach/7db.c index e367c8255..f12432262 100644 --- a/sys/src/libmach/7db.c +++ b/sys/src/libmach/7db.c @@ -49,8 +49,8 @@ Machdata arm64mach = riscframe, /* Frame finder */ arm64excep, /* print exception */ 0, /* breakpoint fixup */ - 0, /* single precision float printer */ - 0, /* double precision float printer */ + leieeesftos, /* single precision float printer */ + leieeedftos, /* double precision float printer */ arm64foll, /* following addresses */ arm64inst, /* print instruction */ arm64das, /* dissembler */ @@ -258,6 +258,12 @@ static Opcode opcodes[] = "11010101000000110100xxxx11111111", "MSR", "$%x,DAIFClr", "11010101000YYYYYYYYYYYYYYYYddddd", "MSR", "R%d,%Y", "11010101001YYYYYYYYYYYYYYYYddddd", "MRS", "%Y,R%d", + "FF11110101uuuuuuuuuuuu11111ddddd", "FMOV%F", "%u(SP),F%d", + "FF11110101uuuuuuuuuuuunnnnnddddd", "FMOV%F", "%u(R%n),F%d", + "FF111100010ooooooooo0011111ddddd", "FMOV%F", "%o(SP),F%d", + "FF111100010ooooooooo00nnnnnddddd", "FMOV%F", "%o(R%n),F%d", + "W0011110ZZ111000000000nnnnnddddd", "FCVTZS%Z%W", "F%n,R%d", + "W0011110ZZ111001000000nnnnnddddd", "FCVTZU%Z%W", "F%n,R%d", "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", "WORD", "$%x", }; @@ -471,6 +477,11 @@ format(char *mnemonic, Instr *i, char *f) *i->curr++ = "BHW"[u]; break; + case 'F': // FP width + u &= 3; + *i->curr++ = "BHSD"[u]; + break; + case 'd': // Register Numbers case 'n': case 'a': @@ -592,6 +603,10 @@ format(char *mnemonic, Instr *i, char *f) } break; + case 'Z': // FP type + *i->curr++ = "SD?H"[u]; + break; + case '\0': *i->curr++ = '%'; return; |