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The idea is that when we reboot, we zero out
memory written by processes that have the private
flag set (such as factotum and keyfs), and also
clear the secrmem pool, which contains TLS keys
and the state of the random number generator.
This is so the newly booted kernel or firmware
will not find these secret keys in memory.
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We want to support the internal emmc device on the reform,
which has a different initialization sequence from SDcard.
The problem is, all mmc controller drivers where using
the command index to derive the command properties.
The command index's interpretation depends on the
command set. And MMC has different commands then SD.
Also, there are the APP_CMD escaped commands which
drivers then tried to recover the state...
All of this is total nonsense... The controller drivers
should not care and the command properties should
be maintained by port/sdmmc.c.
So we pass the command as a struct SDiocmd, which
has all the properties (command index, response type,
data transfer mode... and even a string for debugging).
The controller just converts this into register values
and just executes the commands.
Next, the controller drivers shouldnt snoop on the
commands and then try to apply bus and frequency
switching on their own. This is now made explicit by
having SDio.bus(io, width, speed) function.
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Submitted by Matt:
*Explain the problem that your change solves. Explain why your change
solves the problem well.*
The problem is that when using 9front on an Rpi3/Rpi4, on a revision 2
board, in bcm scheme, you cannot use GPIO5 nor GPIO6. If you look at the
pinout, https://pinout.xyz/pinout/, you can see GPIO5 and GPIO6 are both
GPIO pins - so, you should be able to use them. As you can see in the
patch, "5" and "6" were both missing from the bcmtableR2 definition. The
changes noted above fix this issue by adding GPIO5 ("5") and GPIO6 ("6")
to the bcmtableR2 definition. I specifically only addressed r2 boards b/c I
don't have an r1 board and don't want to make any speculations.
* If applicable, explain how you tested the patch, and give us a way of
reproducing the issue.*
I tested this / you can reproduce this by:
- Trying using GPIO5 and GPIO6 without the patch. You can do this by:
bind -a '#G' /dev
cd /dev/gpio
echo 'scheme bcm' > ctl
echo 'function out 5' > ctl
echo 'function out 6' > ctl
read -c 1 5
read -c 1 6
- Note that the `read` command above reads '0' from file 5 and from file 6.
- Now try to change the GPIO pins from 0 (off) to 1 (on)
echo '1' > 5
echo '1' > 6
read -c 1 5
read -c 1 6
- Note that the pins still read '0'
- Now, apply the patch and repeat the steps above. Except, after you `echo
'1' > 5` and `echo '1' > 6`, and then read files "5" and "6", you will see
that the pins now read "1" as intended.
Thanks,
Matt
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remove the global sdio struct and add a addmmcio() function
for drivers to register their controllers.
there is a SDio.aux pointer now where controller drivers
can stash a pointer to their private data.
SDio.init() also can signal that it wants to be called
again for more controllers by returning > 0 (see pc/pmmc.c).
this is in preparation for supporting the internal mmc
device in the mnt-reform which is hooked up to usdhc1.
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The kernel stack is now above the Proc structure,
so the explicit kstack pointer can be eliminated.
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procs come from the dynamic pools, so we don't need
to remove the memory used by possible procs from the
total available.
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Treallocate the small data structures around procs eagerly,
but use malloc to allocate the large proc data structures
when we need them, which allows us to scale to many more procs.
There are still many scalability bottlenecks, so we only crank
up the nproc limit by a little bit this time around, and crank
it up more as we optimize more.
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To avoid a MAXMACH limit of 32 and make
txtflush into an array for the bitmap.
Provide portable macros for testing and clearing
the bits: needtxtflush(), donetxtflush().
On pc/pc64, define inittxtflush()/settxtflush()
as no-op macros, avoiding the storage overhead of
the txtflush array alltogether.
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SSL is implemented by devssl. It's extremely
obsolete by now, and is not used anywhere but
cpu, import, and oexportfs.
This change strips out the devssl bits, but
does not (yet) remove the code from libsec.
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*emmc2bus kernel parameter
/*
* emmc2 has different DMA constraints based on SoC revisions. It was
* moved into its own bus, so as for RPi4's firmware to update them.
* The firmware will find whether the emmc2bus alias is defined, and if
* so, it'll edit the dma-ranges property below accordingly.
*/
emmc2bus: emmc2bus {
compatible = "simple-bus";
ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>;
dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>;
emmc2: mmc@7e340000 {
compatible = "brcm,bcm2711-emmc2";
reg = <0x0 0x7e340000 0x100>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clocks BCM2711_CLOCK_EMMC2>;
status = "disabled";
};
};
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Remove unused fields and factor common fields into a
new PMach struct in port/portdat.h.
The fields machno, splpc and proc are not moved to
PMach as they are part of the known offsets from
assembly (l.s).
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p.kosyh writes:
Hello! I finally bought rpi4 4Gb specially for 9front. It seems,
that default bpp of framebuffer is 16. I changed it to 24 (via
cmdline.txt and config.txt) and found, that rendering is much faster!
(May be due removing overheads in 16->24 conversions?)
But on rpi4 r and b channels are swapped. So, i changed BGR24 to
RGB24 in bcm/screen.c and now it works fine!
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On the pi400, the xhci reset firmware mailbox request
assumes that the pci windows match the ones specified
in the device tree. The inbound window (pcidmawin)
also varies now depending on the amount of memory
installed.
It is all pretty ridiculous, as the firmware could as
well just read the pci controllers hardware register
to determine the window configuration and the os could
keep a nice simple 1:1 mapping (with pci dma addresses
== physical addresses).
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Previously, mmurelease() was always called with
palloc spinlock held.
This is unneccesary for some mmurelease()
implementations as they wont release pages
to the palloc pool.
This change removes pagechainhead() and
pagechaindone() and replaces them with just
freepages() call, which aquires the palloc
lock internally as needed.
freepages() avoids holding the palloc lock
while walking the linked list of pages,
avoding some lock contention.
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we might as well handle the per process cycle
counter in the portable part instead of duplicating the code
in every arch and have inconsistent implementations.
we now have a portable kenter() and kexit() function,
that is ment to be used in trap/syscall from user,
which updates the counters.
some kernels missed initializing Mach.cyclefreq.
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On the 8GB variant of the raspberry pi 4,
the eeprom chip for the xhci controller is missing and
instead loaded from sdram (by the gpu firmware).
for this, the gpu firmware needs to be notified of
the xhci controllers pci bus address (after reset)
that was assigned by our pci enumeration code.
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size detection (thanks kenji)
looks like linux changed the device tree names for
the memory node:
https://github.com/raspberrypi/linux/commit/4b17654f51fd87c42cda3217b0863e6aa1df49b9#diff-ac03c9402b807c11d42edc9e8d03dfc7
this fixes the memory size detection with latest firmware
on raspberry pi4-b (4GB) for kenji.
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The swcursor used a 32x32 image for saving/restoring
screen contents for no reason.
Add a doflush argument to swcursorhide(), so that
disabling software cursor with a double buffered
softscreen is properly hidden. The doflush parameter
should be set to 0 in all other cases as swcursordraw()
will flushes both (current and previours) locations.
Make sure swcursorinit() and swcursorhide() clear the
visibility flag, even when gscreen is nil.
Remove the cursor locking and just do everything within
the drawlock. All cursor functions such as curson(),
cursoff() and setcursor() will be called drawlock
locked. This also means &cursor can be read.
Fix devmouse cursor reads and writes. We now have the
global cursor variable that is only modified under
the drawlock. So copy under drawlock.
Move the pc software cursor implementation into vgasoft
driver, so screen.c does not need to handle it as
a special case.
Remove unused functions such as drawhasclients().
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replace machine specific userinit() by a portable
implemntation that uses kproc() to create the first
process. the initcode text is mapped using kmap(),
so there is no need for machine specific tmpmap()
functions.
initcode stack preparation should be done in init0()
where the stack is mapped and can be accessed directly.
replacing the machine specific userinit() allows some
big simplifications as sysrfork() and kproc() are now
the only callers of newproc() and we can avoid initializing
fields that we know are being initialized by these
callers.
rename autogenerated init.h and reboot.h headers.
the initcode[] and rebootcode[] blobs are now in *.i
files and hex generation was moved to portmkfile. the
machine specific mkfile only needs to specify how to
build rebootcode.out and initcode.out.
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the change to support no-execute bits broke the original
raspberry pi1, as it uses backwards compatible page table
format.
to use the XN bit, subpage AP bits have to be disabled
using the XP bit in CP15 Control Register c1 Bit 23.
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fault() now has an additional pc argument that is
used to detect fault on a non-executable segment.
that is, we check on read fault if the segment
has the SG_NOEXEC attribute and the program counter
is within faulting page.
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add PTECACHED bits
a portable SG_NOEXEC segment attribute was added to allow
non-executable (physical) segments. which will set the
PTENOEXEC bits for putmmu().
in the future, this can be used to make non-executable
stack / bss segments.
the SG_DEVICE attribute was added to distinguish between
mmio regions and uncached memory. only matterns on arm64.
on arm, theres the issue that PTEUNCACHED would have
no bits set when using the hardware bit definitions.
this is the reason bcm, kw, teg2 and omap kernels use
arteficial PTE constants. on zynq, the XN bit was used
as a hack to give PTEUNCACHED a non-zero value and when
the bit is clear then cache attributes where added to
the pte.
to fix this, PTECACHED constant was added.
the portable mmu code in fault.c will now explicitely set
PTECACHED bits for cached memory and PTEUNCACHED for
uncached memory. that way the hardware bit definitions
can be used everywhere.
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aliasing, implement vmap() proper
on the 2GB and 4GB raspberry pi 4 variants, there are two
memory regions for ram:
[0x00000000..0x3e600000)
[0x40000000..0xfc000000)
the framebuffer is somewhere at the end of the first
GB of memory.
to handle these, we append the region base and limit
of the second region to *maxmem= like:
*maxmem=0x3e600000 0x40000000 0xfc000000
the mmu code has been changed to have non-existing
ram unmapped and mmukmap() now uses small 64K pages
instead of 512GB pages to avoid aliasing (framebuffer).
the VIRTPCI mapping has been removed as we now have
a proper vmap() implementation which assigns vritual
addresses automatically.
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make early boot messages available by writing out
kmesg.buf after uart and screen initialization.
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according to the following linux change, BCM2711 uses a different
method for changing pullup/down mode:
https://github.com/raspberrypi/linux/commit/abcfd092860760087b87acbdda0963fe7906839c#diff-cf078559c38543ac72c5db99323e236d
gpiomeminit() was broken, using virtual address for the gpio physseg
instead of the physical one.
cleanup the code, avoid repetition by declaring static u32int *regs
variable. make local variable names consistent.
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cache-line-size aligned buffer
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the raspberry pi 4 has a new interrupt controller and
pci support, so get rid of intrenable() macro and
properly make intrenable function with tbdf argument.
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configurable in Soc.virtio and Soc.iosize
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the new raspberry pi 4 firmware for arm64 seems to have
broken atag support. so we now parse the device tree
structure to get the bootargs and memory configuration.
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