1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
|
/*
* omap3530 system dma controller
*
* terminology: a block consist of frame(s), a frame consist of elements
* (uchar, ushort, or ulong sized).
*/
#include "u.h"
#include "../port/lib.h"
#include "mem.h"
#include "dat.h"
#include "fns.h"
#include "io.h"
#include "../port/error.h"
#include "../port/netif.h"
enum {
Nirq = 4,
Baseirq = 12,
Nchan = 32,
};
/*
* has a sw reset bit
* dma req lines 1, 2, 6, 63 are available for `system expansion'
*/
typedef struct Regs Regs;
typedef struct Dchan Dchan;
struct Regs {
uchar _pad0[8];
/* bitfield of intrs pending, by Dchan; write 1s to clear */
ulong irqsts[Nirq];
ulong irqen[Nirq]; /* bitfield of intrs enabled, by Dchan */
ulong syssts; /* 1<<0 is Resetdone */
ulong syscfg; /* 1<<1 is Softreset */
uchar _pad1[0x64 - 0x30];
ulong caps[5]; /* caps[1] not defined */
ulong gcr; /* knobs */
ulong _pad2;
struct Dchan {
ulong ccr; /* chan ctrl: incr, etc. */
ulong clnkctrl; /* link ctrl */
ulong cicr; /* intr ctrl */
ulong csr; /* status */
ulong csdp; /* src & dest params */
ulong cen; /* element # */
ulong cfn; /* frame # */
ulong cssa; /* src start addr */
ulong cdsa; /* dest start addr */
ulong csei; /* src element index */
ulong csfi; /* src frame index | pkt size */
ulong cdei; /* dest element index */
ulong cdfi; /* dest frame index | pkt size */
ulong csac; /* src addr value (read-only?) */
ulong cdac; /* dest addr value */
ulong ccen; /* curr transferred element # (in frame) */
ulong ccfn; /* curr transferred frame # (in xfer) */
ulong color;
uchar _pad3[24];
} chan[Nchan];
};
enum {
/* cicr/csr bits */
Blocki = 1 << 5,
/* ccr bits */
Enable = 1 << 7,
};
typedef struct Xfer Xfer;
static struct Xfer {
Rendez *rend;
int *done; /* flag to set on intr */
} xfer[Nirq];
int
isdmadone(int irq)
{
Dchan *cp;
Regs *regs = (Regs *)PHYSSDMA;
cp = regs->chan + irq;
return cp->csr & Blocki;
}
static void
dmaintr(Ureg *, void *a)
{
int i = (int)a; /* dma request & chan # */
Dchan *cp;
Regs *regs = (Regs *)PHYSSDMA;
assert(i >= 0 && i < Nirq);
*xfer[i].done = 1;
assert(xfer[i].rend != nil);
wakeup(xfer[i].rend);
cp = regs->chan + i;
if(!(cp->csr & Blocki))
iprint("dmaintr: req %d: Blocki not set; csr %#lux\n",
i, cp->csr);
cp->csr |= cp->csr; /* extinguish intr source */
coherence();
regs->irqsts[i] = regs->irqsts[i]; /* extinguish intr source */
coherence();
regs->irqen[i] &= ~(1 << i);
coherence();
xfer[i].rend = nil;
coherence();
}
void
zerowds(ulong *wdp, int cnt)
{
while (cnt-- > 0)
*wdp++ = 0;
}
static int
istestdmadone(void *arg)
{
return *(int *)arg;
}
void
dmainit(void)
{
int n;
char name[16];
Dchan *cp;
Regs *regs = (Regs *)PHYSSDMA;
if (probeaddr((uintptr)®s->syssts) < 0)
panic("dmainit: no syssts reg");
regs->syssts = 0;
coherence();
regs->syscfg |= 1<<1; /* Softreset */
coherence();
while(!(regs->syssts & (1<<0))) /* Resetdone? */
;
for (n = 0; n < Nchan; n++) {
cp = regs->chan + n;
cp->ccr = 0;
cp->clnkctrl = 0;
cp->cicr = 0;
cp->csr = 0;
cp->csdp = 0;
cp->cen = cp->cfn = 0;
cp->cssa = cp->cdsa = 0;
cp->csei = cp->csfi = 0;
cp->cdei = cp->cdfi = 0;
// cp->csac = cp->cdac = 0; // ro
cp->ccen = cp->ccfn = 0;
cp->color = 0;
}
zerowds((void *)regs->irqsts, sizeof regs->irqsts / sizeof(ulong));
zerowds((void *)regs->irqen, sizeof regs->irqen / sizeof(ulong));
coherence();
regs->gcr = 65; /* burst size + 1 */
coherence();
for (n = 0; n < Nirq; n++) {
snprint(name, sizeof name, "dma%d", n);
intrenable(Baseirq + n, dmaintr, (void *)n, nil, name);
}
}
enum {
Testbyte = 0252,
Testsize = 256,
Scratch = MB,
};
/*
* try to confirm sane operation
*/
void
dmatest(void)
{
int n, done;
uchar *bp;
static ulong pat = 0x87654321;
static Rendez trendez;
if (up == nil)
panic("dmatest: up not set yet");
bp = (uchar *)KADDR(PHYSDRAM + 128*MB);
memset(bp, Testbyte, Scratch);
done = 0;
dmastart((void *)PADDR(bp), Postincr, (void *)PADDR(&pat), Const,
Testsize, &trendez, &done);
sleep(&trendez, istestdmadone, &done);
cachedinvse(bp, Scratch);
if (((ulong *)bp)[0] != pat)
panic("dmainit: copied incorrect data %#lux != %#lux",
((ulong *)bp)[0], pat);
for (n = Testsize; n < Scratch && bp[n] != Testbyte; n++)
;
if (n >= Scratch)
panic("dmainit: ran wild over memory, clobbered ≥%,d bytes", n);
if (bp[n] == Testbyte && n != Testsize)
iprint("dma: %d-byte dma stopped after %d bytes!\n",
Testsize, n);
}
/* addresses are physical */
int
dmastart(void *to, int tmode, void *from, int fmode, uint len, Rendez *rend,
int *done)
{
int irq, chan;
uint ruplen;
Dchan *cp;
Regs *regs = (Regs *)PHYSSDMA;
static Lock alloclck;
/* allocate free irq (and chan) */
ilock(&alloclck);
for (irq = 0; irq < Nirq && xfer[irq].rend != nil; irq++)
;
if (irq >= Nirq)
panic("dmastart: no available irqs; too many concurrent dmas");
chan = irq;
xfer[irq].rend = rend; /* for wakeup at intr time */
xfer[irq].done = done;
*done = 0;
iunlock(&alloclck);
ruplen = ROUND(len, sizeof(ulong));
assert(to != from);
cp = regs->chan + chan;
cp->ccr &= ~Enable; /* paranoia */
cp->cicr = 0;
regs->irqen[irq] &= ~(1 << chan);
coherence();
cp->csdp = 2; /* 2 = log2(sizeof(ulong)) */
cp->cssa = (uintptr)from;
cp->cdsa = (uintptr)to;
cp->ccr = tmode << 14 | fmode << 12;
cp->csei = cp->csfi = cp->cdei = cp->cdfi = 1;
cp->cen = ruplen / sizeof(ulong); /* ulongs / frame */
cp->cfn = 1; /* 1 frame / xfer */
cp->cicr = Blocki; /* intr at end of block */
regs->irqen[irq] |= 1 << chan;
coherence();
cp->ccr |= Enable; /* fire! */
coherence();
return irq;
}
|
