1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
|
/*
* arm co-processors
* mainly to cope with arm hard-wiring register numbers into instructions.
*
* CP15 (system control) is the one that gets used the most in practice.
* these routines must be callable from KZERO space or the 0 segment.
*/
#include "u.h"
#include "../port/lib.h"
#include "mem.h"
#include "dat.h"
#include "fns.h"
#include "io.h"
#include "arm.h"
enum {
/* alternates: 0xe12fff1e BX (R14); last e is R14 */
/* 0xe28ef000 B 0(R14); second e is R14 (ken) */
Retinst = 0xe1a0f00e, /* MOV R14, R15 */
Opmask = MASK(3),
Regmask = MASK(4),
};
typedef ulong (*Pufv)(void);
typedef void (*Pvfu)(ulong);
static void
setupcpop(ulong instr[2], ulong opcode, int cp, int op1, int crn, int crm,
int op2)
{
ulong instrsz[2];
op1 &= Opmask;
op2 &= Opmask;
crn &= Regmask;
crm &= Regmask;
cp &= Regmask;
instr[0] = opcode | op1 << 21 | crn << 16 | cp << 8 | op2 << 5 | crm;
instr[1] = Retinst;
cachedwbse(instr, sizeof instrsz);
cacheiinv();
}
ulong
cprd(int cp, int op1, int crn, int crm, int op2)
{
int s, r;
volatile ulong instr[2];
Pufv fp;
s = splhi();
/*
* MRC. return value will be in R0, which is convenient.
* Rt will be R0.
*/
setupcpop(instr, 0xee100010, cp, op1, crn, crm, op2);
fp = (Pufv)instr;
r = fp();
splx(s);
return r;
}
void
cpwr(int cp, int op1, int crn, int crm, int op2, ulong val)
{
int s;
volatile ulong instr[2];
Pvfu fp;
s = splhi();
setupcpop(instr, 0xee000010, cp, op1, crn, crm, op2); /* MCR, Rt is R0 */
fp = (Pvfu)instr;
fp(val);
coherence();
splx(s);
}
ulong
cprdsc(int op1, int crn, int crm, int op2)
{
return cprd(CpSC, op1, crn, crm, op2);
}
void
cpwrsc(int op1, int crn, int crm, int op2, ulong val)
{
cpwr(CpSC, op1, crn, crm, op2, val);
}
/* floating point */
/* fp coproc control */
static void
setupfpctlop(ulong instr[2], int opcode, int fpctlreg)
{
ulong instrsz[2];
fpctlreg &= Nfpctlregs - 1;
instr[0] = opcode | fpctlreg << 16 | 0 << 12 | CpFP << 8;
instr[1] = Retinst;
cachedwbse(instr, sizeof instrsz);
cacheiinv();
}
ulong
fprd(int fpreg)
{
int s, r;
volatile ulong instr[2];
Pufv fp;
if (!m->fpon) {
dumpstack();
panic("fprd: cpu%d fpu off", m->machno);
}
s = splhi();
/*
* VMRS. return value will be in R0, which is convenient.
* Rt will be R0.
*/
setupfpctlop(instr, 0xeef00010, fpreg);
fp = (Pufv)instr;
r = fp();
splx(s);
return r;
}
void
fpwr(int fpreg, ulong val)
{
int s;
volatile ulong instr[2];
Pvfu fp;
/* fpu might be off and this VMSR might enable it */
s = splhi();
setupfpctlop(instr, 0xeee00010, fpreg); /* VMSR, Rt is R0 */
fp = (Pvfu)instr;
fp(val);
coherence();
splx(s);
}
/* fp register access; don't bother with single precision */
static void
setupfpop(ulong instr[2], int opcode, int fpreg)
{
ulong instrsz[2];
instr[0] = opcode | 0 << 16 | (fpreg & (16 - 1)) << 12;
if (fpreg >= 16)
instr[0] |= 1 << 22; /* high bit of dfp reg # */
instr[1] = Retinst;
cachedwbse(instr, sizeof instrsz);
cacheiinv();
}
ulong
fpsavereg(int fpreg, uvlong *fpp)
{
int s, r;
volatile ulong instr[2];
ulong (*fp)(uvlong *);
if (!m->fpon)
panic("fpsavereg: cpu%d fpu off", m->machno);
s = splhi();
/*
* VSTR. pointer will be in R0, which is convenient.
* Rt will be R0.
*/
setupfpop(instr, 0xed000000 | CpDFP << 8, fpreg);
fp = (ulong (*)(uvlong *))instr;
r = fp(fpp);
splx(s);
coherence();
return r; /* not too meaningful */
}
void
fprestreg(int fpreg, uvlong val)
{
int s;
volatile ulong instr[2];
void (*fp)(uvlong *);
if (!m->fpon)
panic("fprestreg: cpu%d fpu off", m->machno);
s = splhi();
setupfpop(instr, 0xed100000 | CpDFP << 8, fpreg); /* VLDR, Rt is R0 */
fp = (void (*)(uvlong *))instr;
fp(&val);
coherence();
splx(s);
}
|
