1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
|
#include "u.h"
#include "../port/lib.h"
#include "mem.h"
#include "dat.h"
#include "fns.h"
#include "io.h"
#include "../port/pci.h"
typedef struct {
ulong cap;
ulong ctl;
} Capctl;
typedef struct {
Capctl dev;
Capctl link;
Capctl slot;
} Devlinkslot;
/* capability list id 0x10 is pci-e */
typedef struct Pci Pci;
struct Pci {
/* pci-compatible config */
/* what io.h calls type 0 & type 1 pre-defined header */
ulong id;
ulong cs;
ulong revclass;
ulong misc; /* cache line size, latency timer, header type, bist */
ulong bar[2]; /* always 0 on tegra 2 */
/* types 1 & 2 pre-defined header */
ulong bus;
ulong ioaddrs;
ulong memaddrs;
ulong prefmem;
ulong prefbasehi;
ulong preflimhi;
/* type 2 pre-defined header only */
ulong ioaddrhi;
ulong cfgcapoff; /* offset in cfg. space to cap. list (0x40) */
ulong rom;
ulong intr; /* PciINT[LP] */
/* subsystem capability regs */
ulong subsysid;
ulong subsyscap;
/* */
Capctl pwrmgmt;
/* msi */
ulong msictlcap;
ulong msimsgaddr[2]; /* little-endian */
ulong msimsgdata;
/* pci-e cap. */
uchar _pad0[0x80-0x60];
ulong pciecap;
Devlinkslot port0;
ulong rootctl;
ulong rootsts;
Devlinkslot port1;
/* 0xbc */
};
enum {
/* offsets from soc.pci */
Port0 = 0,
Port1 = 0x1000,
Pads = 0x3000,
Afi = 0x3800,
Aficfg = Afi + 0xac,
Cfgspace = 0x4000,
Ecfgspace = 0x104000,
/* cs bits */
Iospace = 1<<0,
Memspace = 1<<1,
Busmaster = 1<<2,
/* Aficfg bits */
Fpcion = 1<<0,
};
struct Pcictlr {
union {
uchar _padpci[0x1000];
Pci;
} ports[2];
uchar _padpads[0x1000];
uchar pads[0x800];
uchar afi[0x800];
ulong cfg[0x1000];
ulong extcfg[0x1000];
};
static int pcicfgmode = -1;
static int pcimaxbno = 1; /* was 7; only 2 pci buses; touching 3rd hangs */
static Pcidev* pciroot;
extern void rtl8169interrupt(Ureg*, void* arg);
/* not used yet */
static void
pciintr(Ureg *ureg, void *p)
{
rtl8169interrupt(ureg, p); /* HACK */
}
static void
pcicfginit(void)
{
char *p;
Pci *pci = (Pci *)soc.pci;
Pcidev **list;
int bno, n;
/*
* TrimSlice # pci 0 1
* Scanning PCI devices on bus 0 1
* BusDevFun VendorId DeviceId Device Class Sub-Class
* _____________________________________________________________
* 00.00.00 0x10de 0x0bf0 Bridge device 0x04
* 01.00.00 0x10ec 0x8168 Network controller 0x00
*
* thus pci bus 0 has a bridge with, perhaps, an ide/sata ctlr behind,
* and pci bus 1 has the realtek 8169 on it:
*
* TrimSlice # pci 1 long
* Scanning PCI devices on bus 1
*
* Found PCI device 01.00.00:
* vendor ID = 0x10ec
* device ID = 0x8168
* command register = 0x0007
* status register = 0x0010
* revision ID = 0x03
* class code = 0x02 (Network controller)
* sub class code = 0x00
* programming interface = 0x00
* cache line = 0x08
* base address 0 = 0x80400001 config
* base address 1 = 0x00000000 (ext. config)
* base address 2 = 0xa000000c "downstream"
* base address 3 = 0x00000000 (prefetchable)
* base address 4 = 0xa000400c not "
* base address 5 = 0x00000000 (unused)
*/
n = pci->id >> 16;
if (((pci->id & MASK(16)) != Vnvidia || (n != 0xbf0 && n != 0xbf1)) &&
(pci->id & MASK(16)) != Vrealtek) {
print("no pci controller at %#p\n", pci);
return;
}
if (0)
iprint("pci: %#p: nvidia, rev %#ux class %#6.6lux misc %#8.8lux\n",
pci, (uchar)pci->revclass, pci->revclass >> 8,
pci->misc);
pci->cs &= Iospace;
pci->cs |= Memspace | Busmaster;
coherence();
pcicfgmode = 1;
pcimaxdno = 15; /* for trimslice */
fmtinstall('T', tbdffmt);
if(p = getconf("*pcimaxbno")){
n = strtoul(p, 0, 0);
if(n < pcimaxbno)
pcimaxbno = n;
}
if(p = getconf("*pcimaxdno")){
n = strtoul(p, 0, 0);
if(n < pcimaxdno)
pcimaxdno = n;
}
list = &pciroot;
/* was bno = 0; trimslice needs to start at 1 */
for(bno = 1; bno <= pcimaxbno; bno++) {
bno = pciscan(bno, list);
while(*list)
list = &(*list)->link;
}
if(getconf("*pcihinv"))
pcihinv(pciroot);
}
enum {
Afiintrcode = 0xb8,
};
void
pcieintrdone(void) /* dismiss pci-e intr */
{
ulong *afi;
afi = (ulong *)(soc.pci + Afi);
afi[Afiintrcode/sizeof *afi] = 0; /* magic */
coherence();
}
/*
* whole config space for tbdf should be at (return address - rno).
*/
static void *
tegracfgaddr(int tbdf, int rno)
{
uintptr addr;
addr = soc.pci + (rno < 256? Cfgspace: Ecfgspace) + BUSBDF(tbdf) + rno;
// if (BUSBNO(tbdf) == 1)
// addr += Port1;
return (void *)addr;
}
int
pcicfgrw8(int tbdf, int rno, int data, int read)
{
void *addr;
addr = tegracfgaddr(tbdf, rno);
if(read)
data = *(uchar *)addr;
else
*(uchar *)addr = data;
return data;
}
int
pcicfgrw16(int tbdf, int rno, int data, int read)
{
void *addr;
addr = tegracfgaddr(tbdf, rno);
if(read)
data = *(ushort *)addr;
else
*(ushort *)addr = data;
return data;
}
int
pcicfgrw32(int tbdf, int rno, int data, int read)
{
vlong v;
void *addr;
addr = tegracfgaddr(tbdf, rno);
v = probeaddr((uintptr)addr);
if (v < 0)
return -1;
if(read)
data = *(ulong *)addr;
else
*(ulong *)addr = data;
return data;
}
void
pciteglink(void)
{
pcicfginit();
}
|