diff options
| author | Michael Forney <mforney@mforney.org> | 2022-11-12 01:11:09 +0000 |
|---|---|---|
| committer | Ori Bernstein <ori@eigenstate.org> | 2022-11-12 01:11:09 +0000 |
| commit | d09e5a7af724cbb2df7a066a805cf6c8303a4b39 (patch) | |
| tree | 06589833e7529bbcdca2dac157ada3b0fb0b6386 | |
| parent | 2380532ff58c2afd666bc9c40dbb7a65c77c204c (diff) | |
usbxhci: wait for reset to complete before continuing initialization
The xhci spec says that the HCRST bit is cleared once the reset is
complete, and that no operational or runtime registers shall be
written while the bit is set.
Waiting for the reset to complete fixes initialization of some host
controllers, such as the ASMedia ASM1142, which otherwise enter an
endless init-recover loop.
Also, add a comment about the reason for the 1ms delay. This appears
to work around a system hang bug in intel chipsets through the 400
series (see errata 15 in [0]).
[0] https://cdrdv2-public.intel.com/620856/620856-009.pdf
| -rw-r--r-- | sys/src/9/port/usbxhci.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/sys/src/9/port/usbxhci.c b/sys/src/9/port/usbxhci.c index 90abb2969..37a86e987 100644 --- a/sys/src/9/port/usbxhci.c +++ b/sys/src/9/port/usbxhci.c @@ -481,7 +481,10 @@ init(Hci *hp) tsleep(&up->sleep, return0, nil, 10); ctlr->opr[USBCMD] = HCRST; + /* some intel controllers require 1ms delay after reset */ delay(1); + for(i=0; (ctlr->opr[USBCMD] & HCRST) != 0 && i<100; i++) + tsleep(&up->sleep, return0, nil, 10); for(i=0; (ctlr->opr[USBSTS] & (CNR|HCH)) != HCH && i<100; i++) tsleep(&up->sleep, return0, nil, 10); |