diff options
| author | cinap_lenrek <cinap_lenrek@felloff.net> | 2019-05-03 22:02:07 +0200 |
|---|---|---|
| committer | cinap_lenrek <cinap_lenrek@felloff.net> | 2019-05-03 22:02:07 +0200 |
| commit | eb4bd4aa3ec7308fd4dea9810c7d2de1f5977288 (patch) | |
| tree | 066203960cad87945021c3222b011e627b2af364 | |
| parent | 3ca395a36c3c1b098433c7a47106e76f00aee324 (diff) | |
bcm: move fiq saved pc adjust into lexception.s so it can be shared with arm64
| -rw-r--r-- | sys/src/9/bcm/irq.c | 4 | ||||
| -rw-r--r-- | sys/src/9/bcm/lexception.s | 1 | ||||
| -rw-r--r-- | sys/src/9/bcm/trap.c | 1 |
3 files changed, 3 insertions, 3 deletions
diff --git a/sys/src/9/bcm/irq.c b/sys/src/9/bcm/irq.c index f93dcd38c..33c1d820b 100644 --- a/sys/src/9/bcm/irq.c +++ b/sys/src/9/bcm/irq.c @@ -83,6 +83,7 @@ irq(Ureg* ureg) Vctl *v; int clockintr; + m->intr++; clockintr = 0; for(v = vctl[m->machno]; v != nil; v = v->next) if((*v->reg & v->mask) != 0){ @@ -103,11 +104,10 @@ fiq(Ureg *ureg) { Vctl *v; + m->intr++; v = vfiq; if(v == nil) panic("cpu%d: unexpected item in bagging area", m->machno); - m->intr++; - ureg->pc -= 4; coherence(); v->f(ureg, v->a); coherence(); diff --git a/sys/src/9/bcm/lexception.s b/sys/src/9/bcm/lexception.s index bb1693d7b..eb82e82b0 100644 --- a/sys/src/9/bcm/lexception.s +++ b/sys/src/9/bcm/lexception.s @@ -187,6 +187,7 @@ TEXT _vfiq(SB), 1, $-4 /* FIQ */ MOVW $PsrMfiq, R8 /* trap type */ MOVW SPSR, R9 /* interrupted psr */ MOVW R14, R10 /* interrupted pc */ + SUB $4, R10 /* ureg->pc -= 4 */ MOVM.DB.W [R8-R10], (R13) /* save in ureg */ MOVM.DB.S [R0-R14], (R13) /* save interrupted regs */ SUB $(15*4), R13 diff --git a/sys/src/9/bcm/trap.c b/sys/src/9/bcm/trap.c index 6b15b577d..8522eacd2 100644 --- a/sys/src/9/bcm/trap.c +++ b/sys/src/9/bcm/trap.c @@ -188,7 +188,6 @@ trap(Ureg *ureg) break; case PsrMirq: clockintr = irq(ureg); - m->intr++; break; case PsrMabt: /* prefetch fault */ x = ifsrget(); |