diff options
| author | Sigrid Solveig Haflínudóttir <sigrid@ftrv.se> | 2023-04-24 00:34:02 +0000 |
|---|---|---|
| committer | Sigrid Solveig Haflínudóttir <sigrid@ftrv.se> | 2023-04-24 00:34:02 +0000 |
| commit | bbc01d697db5dab5aaad0ad9c9065224aba3dd91 (patch) | |
| tree | 28c67cf9498d91ed83e1bdf2e142110d8d748db6 /sys/src/9 | |
| parent | e93625550dc0beb8b455246e20690ba90d2bbd04 (diff) | |
imx8: add vpu clocks and irq indices, correct a typo (no functional change)
Diffstat (limited to 'sys/src/9')
| -rw-r--r-- | sys/src/9/imx8/ccm.c | 6 | ||||
| -rw-r--r-- | sys/src/9/imx8/io.h | 2 |
2 files changed, 7 insertions, 1 deletions
diff --git a/sys/src/9/imx8/ccm.c b/sys/src/9/imx8/ccm.c index f0a529fcc..8b8f1953a 100644 --- a/sys/src/9/imx8/ccm.c +++ b/sys/src/9/imx8/ccm.c @@ -878,7 +878,7 @@ static Clock clocks[] = { { "sim_main.cm4clk", ARM_M4_CLK_ROOT }, { "sim_main.enetclk", ENET_AXI_CLK_ROOT, 64 }, { "sim_main.mainclk", MAIN_AXI_CLK_ROOT, 66 }, - { "sim_main,mainclk_r", MAIN_AXI_CLK_ROOT, 66 }, + { "sim_main.mainclk_r", MAIN_AXI_CLK_ROOT, 66 }, { "sim_main.per_mclk", AHB_CLK_ROOT, 65 }, { "sim_main.per_sclk", AHB_CLK_ROOT, 67 }, { "sim_main.usdhcclk", NAND_USDHC_BUS_CLK_ROOT, 65 }, @@ -964,6 +964,10 @@ static Clock clocks[] = { { "wdog3.ipg_clk", WDOG_CLK_ROOT, 85 }, { "wdog3.ipg_clk_s", WDOG_CLK_ROOT, 85 }, + { "vpu_g1.clk", VPU_G1_CLK_ROOT, 86 }, + { "vpu_g2.clk", VPU_G2_CLK_ROOT, 90 }, + { "vpu_dec.clk", VPU_BUS_CLK_ROOT, 99 }, + { 0 } }; diff --git a/sys/src/9/imx8/io.h b/sys/src/9/imx8/io.h index d9c171e6d..17e66918e 100644 --- a/sys/src/9/imx8/io.h +++ b/sys/src/9/imx8/io.h @@ -8,6 +8,8 @@ enum { IRQcntpns = PPI+14, IRQlcdif = SPI+5, + IRQvpug1 = SPI+7, + IRQvpug2 = SPI+8, IRQusdhc1 = SPI+22, IRQusdhc2 = SPI+23, |