diff options
| author | Michael Forney <mforney@mforney.org> | 2022-03-05 01:06:20 +0000 |
|---|---|---|
| committer | Michael Forney <mforney@mforney.org> | 2022-03-05 01:06:20 +0000 |
| commit | 0f890140f25324aa076b10f146840f6d7dc85a3a (patch) | |
| tree | 1e2efa218844c709fe937aa16ac6e8f9400ce0fb /sys/src/cmd/aux/vga | |
| parent | d52f25ecdcf1dc8ee8d278c8da44159d82d8dd8f (diff) | |
igfx: fix some typos in comments
Diffstat (limited to 'sys/src/cmd/aux/vga')
| -rw-r--r-- | sys/src/cmd/aux/vga/igfx.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/sys/src/cmd/aux/vga/igfx.c b/sys/src/cmd/aux/vga/igfx.c index 08c7f65f5..5b95ab929 100644 --- a/sys/src/cmd/aux/vga/igfx.c +++ b/sys/src/cmd/aux/vga/igfx.c @@ -65,7 +65,7 @@ struct Trans { Reg vss; /* pipe/trans VSYNCSHIFT_x */ Reg conf; /* pipe/trans CONF_x */ - Reg chicken; /* workarround register */ + Reg chicken; /* workaround register */ Reg dpctl; /* TRANS_DP_CTL_x */ @@ -962,7 +962,7 @@ inittrans(Trans *t, Mode *m) /* clear all but 27:28 frame start delay (initialized by bios) */ t->conf.v &= 3<<27; - /* tans/pipe enable */ + /* trans/pipe enable */ t->conf.v |= 1<<31; /* trans/pipe timing */ @@ -1384,7 +1384,7 @@ loadtrans(Igfx *igfx, Trans *t) sleep(10); } - /* workarround: set timing override bit */ + /* workaround: set timing override bit */ csr(igfx, t->chicken.a, 0, 1<<31); /* enable displayport transcoder */ @@ -1579,7 +1579,7 @@ disabletrans(Igfx *igfx, Trans *t) if((rr(igfx, t->conf.a) & (1<<30)) == 0) break; } - /* workarround: clear timing override bit */ + /* workaround: clear timing override bit */ csr(igfx, t->chicken.a, 1<<31, 0); /* disable dpll */ |