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authorqwx <devnull@localhost>2017-08-23 00:25:39 +0300
committerqwx <devnull@localhost>2017-08-23 00:25:39 +0300
commit174d7e52a3fd4b48bece311415fbdd9e1bb85ccc (patch)
tree9f1760b0279563896898e40c660646d712fae6ee /sys/src/cmd/aux/vga
parentc6359c3090bf0ca958aab17693567e1b00825213 (diff)
igfx: fix cdclk and dpll settings for dual channel lvds on sandybridge
Diffstat (limited to 'sys/src/cmd/aux/vga')
-rw-r--r--sys/src/cmd/aux/vga/igfx.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/sys/src/cmd/aux/vga/igfx.c b/sys/src/cmd/aux/vga/igfx.c
index 40d9c2107..cc595c132 100644
--- a/sys/src/cmd/aux/vga/igfx.c
+++ b/sys/src/cmd/aux/vga/igfx.c
@@ -456,7 +456,7 @@ snarf(Vga* vga, Ctlr* ctlr)
case TypeSNB:
igfx->npipe = 2; /* A,B */
- igfx->cdclk = 300; /* MHz */
+ igfx->cdclk = 400; /* MHz */
goto IVBcommon;
case TypeIVB:
@@ -843,6 +843,10 @@ initdpll(Igfx *igfx, int x, int freq, int port)
dpll->ctrl.v &= ~(3<<24);
if(port == PortLCD){
p2 = 14;
+ if(freq > 112*MHz){
+ p2 >>= 1;
+ dpll->ctrl.v |= (1<<24);
+ }
if(genpll(freq, cref, p2, &m1, &m2, &n, &p1) < 0)
return -1;
} else {