diff options
author | cinap_lenrek <cinap_lenrek@felloff.net> | 2015-01-13 18:04:33 +0100 |
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committer | cinap_lenrek <cinap_lenrek@felloff.net> | 2015-01-13 18:04:33 +0100 |
commit | d115bd0e20fbfdadfb7370a5d12156f1f488e533 (patch) | |
tree | 5166679d9bc52e06c4fdb83bb6e3a26cfc4e07c7 /sys/src/cmd | |
parent | 9f11d4f6899071558e751dc0a9e6651e51d4cf6f (diff) |
igfx: cursor/plane pipe assign is G45 only, add magic dsp a toggle from enable sequence
Diffstat (limited to 'sys/src/cmd')
-rw-r--r-- | sys/src/cmd/aux/vga/igfx.c | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/sys/src/cmd/aux/vga/igfx.c b/sys/src/cmd/aux/vga/igfx.c index 35b8f0915..5f8fe7d8a 100644 --- a/sys/src/cmd/aux/vga/igfx.c +++ b/sys/src/cmd/aux/vga/igfx.c @@ -815,6 +815,8 @@ init(Vga* vga, Ctlr* ctlr) /* plane enable, 32bpp */ p->dsp->cntr.v = (1<<31) | (6<<26); + if(igfx->type == TypeG45) + p->dsp->cntr.v |= x<<24; /* pipe assign */ /* stride must be 64 byte aligned */ p->dsp->stride.v = m->x * (m->z / 8); @@ -829,7 +831,9 @@ init(Vga* vga, Ctlr* ctlr) p->dsp->tileoff.v = 0; /* cursor plane off */ - p->cur->cntr.v = x<<28; + p->cur->cntr.v = 0; + if(igfx->type == TypeG45) + p->cur->cntr.v |= x<<28; /* pipe assign */ p->cur->pos.v = 0; p->cur->base.v = 0; @@ -999,10 +1003,10 @@ disablepipe(Igfx *igfx, int x) /* planes off */ csr(igfx, p->dsp->cntr.a, 1<<31, 0); - csr(igfx, p->dsp->surf.a, ~0, 0); /* arm */ + wr(igfx, p->dsp->surf.a, 0); /* arm */ /* cursor off */ csr(igfx, p->cur->cntr.a, 1<<5 | 7, 0); - csr(igfx, p->cur->base.a, ~0, 0); /* arm */ + wr(igfx, p->cur->base.a, 0); /* arm */ /* display/overlay/cursor planes off */ if(igfx->type == TypeG45) @@ -1064,6 +1068,16 @@ load(Vga* vga, Ctlr* ctlr) for(x = 0; x < igfx->npipe; x++) disablepipe(igfx, x); + if(igfx->type == TypeG45){ + /* toggle dsp a on and off (from enable sequence) */ + csr(igfx, igfx->pipe[0].conf.a, 3<<18, 0); + csr(igfx, igfx->pipe[0].dsp->cntr.a, 0, 1<<31); + wr(igfx, igfx->pipe[0].dsp->surf.a, 0); /* arm */ + csr(igfx, igfx->pipe[0].dsp->cntr.a, 1<<31, 0); + wr(igfx, igfx->pipe[0].dsp->surf.a, 0); /* arm */ + csr(igfx, igfx->pipe[0].conf.a, 0, 3<<18); + } + /* program new clock sources */ loadreg(igfx, igfx->rawclkfreq); loadreg(igfx, igfx->drefctl); |