diff options
| author | cinap_lenrek <cinap_lenrek@felloff.net> | 2015-12-06 20:52:15 +0100 |
|---|---|---|
| committer | cinap_lenrek <cinap_lenrek@felloff.net> | 2015-12-06 20:52:15 +0100 |
| commit | 1a5c8430d20d7ec5cd52c8335af6490ab1dabcf2 (patch) | |
| tree | e24cc27bb656622595136c5a6812b42eca4c8459 /sys/src/libmp | |
| parent | 8d16e980c29535d9d92a4a297077a51207cf93e4 (diff) | |
libmp: fix wrong move instruction for arm vector operations
Diffstat (limited to 'sys/src/libmp')
| -rw-r--r-- | sys/src/libmp/arm/mpvecadd.s | 10 | ||||
| -rw-r--r-- | sys/src/libmp/arm/mpvecdigmuladd.s | 4 | ||||
| -rw-r--r-- | sys/src/libmp/arm/mpvecdigmulsub.s | 4 | ||||
| -rw-r--r-- | sys/src/libmp/arm/mpvecsub.s | 10 |
4 files changed, 14 insertions, 14 deletions
diff --git a/sys/src/libmp/arm/mpvecadd.s b/sys/src/libmp/arm/mpvecadd.s index 931213407..a596e44e2 100644 --- a/sys/src/libmp/arm/mpvecadd.s +++ b/sys/src/libmp/arm/mpvecadd.s @@ -9,22 +9,22 @@ TEXT mpvecadd(SB),$0 B.EQ _add1 SUB R6, R4, R4 _addloop1: - MOVW.WP 4(R0), R1 - MOVW.WP 4(R5), R2 + MOVW.P 4(R0), R1 + MOVW.P 4(R5), R2 CMP $1, R3 ADC.S R2, R1 ADC R8, R8, R3 - MOVW.WP R1, 4(R7) + MOVW.P R1, 4(R7) SUB.S $1, R6 B.NE _addloop1 _add1: CMP R8, R4 B.EQ _addend _addloop2: - MOVW.WP 4(R0), R1 + MOVW.P 4(R0), R1 ADD.S R3, R1 ADC R8, R8, R3 - MOVW.WP R1, 4(R7) + MOVW.P R1, 4(R7) SUB.S $1, R4 B.NE _addloop2 _addend: diff --git a/sys/src/libmp/arm/mpvecdigmuladd.s b/sys/src/libmp/arm/mpvecdigmuladd.s index d006ff81b..64e14ed96 100644 --- a/sys/src/libmp/arm/mpvecdigmuladd.s +++ b/sys/src/libmp/arm/mpvecdigmuladd.s @@ -5,12 +5,12 @@ TEXT mpvecdigmuladd(SB),$0 MOVW $0, R2 _muladdloop: MOVW $0, R1 - MOVW.WP 4(R0), R3 + MOVW.P 4(R0), R3 MULALU R3, R5, (R1, R2) MOVW (R6), R7 ADD.S R2, R7 ADC $0, R1, R2 - MOVW.WP R7, 4(R6) + MOVW.P R7, 4(R6) SUB.S $1, R4 B.NE _muladdloop MOVW (R6), R7 diff --git a/sys/src/libmp/arm/mpvecdigmulsub.s b/sys/src/libmp/arm/mpvecdigmulsub.s index 8340734b6..f94286a9d 100644 --- a/sys/src/libmp/arm/mpvecdigmulsub.s +++ b/sys/src/libmp/arm/mpvecdigmulsub.s @@ -5,13 +5,13 @@ TEXT mpvecdigmulsub(SB),$0 MOVW $0, R2 _mulsubloop: MOVW $0, R1 - MOVW.WP 4(R0), R3 + MOVW.P 4(R0), R3 MULALU R3, R5, (R1, R2) MOVW (R6), R7 SUB.S R2, R7 ADD.CC $1, R1 MOVW R1, R2 - MOVW.WP R7, 4(R6) + MOVW.P R7, 4(R6) SUB.S $1, R4 B.NE _mulsubloop MOVW (R6), R7 diff --git a/sys/src/libmp/arm/mpvecsub.s b/sys/src/libmp/arm/mpvecsub.s index bfcb124ae..c82aa210c 100644 --- a/sys/src/libmp/arm/mpvecsub.s +++ b/sys/src/libmp/arm/mpvecsub.s @@ -9,23 +9,23 @@ TEXT mpvecsub(SB),$0 B.EQ _sub1 SUB R6, R4, R4 _subloop1: - MOVW.WP 4(R0), R1 - MOVW.WP 4(R5), R2 + MOVW.P 4(R0), R1 + MOVW.P 4(R5), R2 CMP R3, R8 SBC.S R2, R1 SBC R8, R8, R3 - MOVW.WP R1, 4(R7) + MOVW.P R1, 4(R7) SUB.S $1, R6 B.NE _subloop1 _sub1: CMP R8, R4 RET.EQ _subloop2: - MOVW.WP 4(R0), R1 + MOVW.P 4(R0), R1 CMP R3, R8 SBC.S R8, R1 SBC R8, R8, R3 - MOVW.WP R1, 4(R7) + MOVW.P R1, 4(R7) SUB.S $1, R4 B.NE _subloop2 RET |