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authoraiju <aiju@phicode.de>2011-05-17 16:51:30 +0000
committeraiju <aiju@phicode.de>2011-05-17 16:51:30 +0000
commitda5d6db6f5bbe2b68288b22dd9b0d4dfa69163db (patch)
tree626b77a60f681e8dcddb4d2b02f19dd0d5d57233 /sys/src
parente7e04b5cbbedfb1411fcc38b7e7f67db98a251c2 (diff)
added support for 32 bit MSI
Diffstat (limited to 'sys/src')
-rw-r--r--sys/src/9/pc/mp.c10
1 files changed, 6 insertions, 4 deletions
diff --git a/sys/src/9/pc/mp.c b/sys/src/9/pc/mp.c
index b74fa1250..f3ca3067f 100644
--- a/sys/src/9/pc/mp.c
+++ b/sys/src/9/pc/mp.c
@@ -883,13 +883,14 @@ mpintrenablex(Vctl* v, int tbdf)
enum {
MSICtrl = 0x02, /* message control register (16 bit) */
MSIAddr = 0x04, /* message address register (64 bit) */
- MSIData = 0x0C, /* message data register (16 bit) */
+ MSIData32 = 0x08, /* message data register for 32 bit MSI (16 bit) */
+ MSIData64 = 0x0C, /* message data register for 64 bit MSI (16 bit) */
};
static int
msiintrenable(Vctl *v)
{
- int tbdf, vno, cap, cpu;
+ int tbdf, vno, cap, cpu, ok64;
Pcidev *pci;
if(getconf("*msi") == nil)
@@ -913,9 +914,10 @@ msiintrenable(Vctl *v)
vno = allocvector();
cpu = mpintrcpu();
+ ok64 = (pcicfgr16(pci, cap + MSICtrl) & (1<<7)) != 0;
pcicfgw32(pci, cap + MSIAddr, (0xFEE << 20) | (cpu << 12));
- pcicfgw32(pci, cap + MSIAddr + 4, 0);
- pcicfgw16(pci, cap + MSIData, vno | (1<<14));
+ if(ok64) pcicfgw32(pci, cap + MSIAddr + 4, 0);
+ pcicfgw16(pci, cap + ok64 ? MSIData64 : MSIData32, vno | (1<<14));
pcicfgw16(pci, cap + MSICtrl, 1);
print("msiintrenable: success with tbdf %.8x, vector %d, cpu %d\n", tbdf, vno, cpu);
v->isr = lapicisr;