1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
|
TEXT setfcr(SB), $4
XORL $(0x3F<<7),RARG /* bits are cleared in csr to enable them */
ANDL $0xFFC0, RARG /* just the fcr bits */
WAIT /* is this needed? */
STMXCSR 0(SP)
MOVL 0(SP), AX
ANDL $~0x3F, AX
ORL RARG, AX
MOVL AX, 0(SP)
LDMXCSR 0(SP)
RET
TEXT getfcr(SB), $4
WAIT
STMXCSR 0(SP)
MOVWLZX 0(SP), AX
ANDL $0xFFC0, AX
XORL $(0x3F<<7),AX
RET
TEXT getfsr(SB), $4
WAIT
STMXCSR 0(SP)
MOVL 0(SP), AX
ANDL $0x3F, AX
RET
TEXT setfsr(SB), $4
ANDL $0x3F, RARG
WAIT
STMXCSR 0(SP)
MOVL 0(SP), AX
ANDL $~0x3F, AX
ORL RARG, AX
MOVL AX, 0(SP)
LDMXCSR 0(SP)
RET
|
