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| author | cinap_lenrek <cinap_lenrek@gmx.de> | 2013-08-27 19:01:41 +0200 |
|---|---|---|
| committer | cinap_lenrek <cinap_lenrek@gmx.de> | 2013-08-27 19:01:41 +0200 |
| commit | 12ecb3e568312f881bfcb22bef71d5a00cfab196 (patch) | |
| tree | 474e271fe28af115b7789dcbb1b0437b1492dd52 /sys/src/cmd/acme/dat.h | |
| parent | d76eccaf88ee1e44211eeff52970221abf9f1acc (diff) | |
usbehci: fix portreset.
Port Reset R/W. 1=Port is in Reset. 0=Port is not in Reset. Default = 0. When
software writes a one to this bit (from a zero), the bus reset sequence as defined in the
USB Specification Revision 2.0 is started. Software writes a zero to this bit to terminate
the bus reset sequence. Software must keep this bit at a one long enough to ensure the
reset sequence, as specified in the USB Specification Revision 2.0, completes. Note:
when software writes this bit to a one, it must also write a zero to the Port Enable bit.
Note that when software writes a zero to this bit there may be a delay before the bit
status changes to a zero. The bit status will not read as a zero until after the reset
has completed.
Diffstat (limited to 'sys/src/cmd/acme/dat.h')
0 files changed, 0 insertions, 0 deletions