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path: root/sys/src/cmd/aux/vga
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2023-04-09DP 1.2 on igfx; EDID wrapping; VGA display connectionsRomano
This patch more fully implements the training patterns for DP 1.2 per the spec, which then allows more monitors to successfully train and therefore connect. In my case it was an LG 34UM68-P. Secondly, this fixes EDID shifting to work with a wider range of values, notably ones which wrap. Lastly, a small correction in vesa.c as to which bits are used to determine available connections.
2022-08-14aux/vga: misc. igfx fixes for displayportqwx
eDP on x250 (broadwell) with a fhd panel now works. external connections via displayport usually still don't. possibly related to link training failures and edid snarfing problems.
2022-08-09igfx: Add support for Xeon E3-1200v3Roberto E. Vargas Caballero
2022-03-05igfx: fix some typos in commentsMichael Forney
2022-03-02igfx: add TypeILK, since it differs slightly from SNBMichael Forney
ILK's LVDS transcoder select field only has 1 bit, like G45.
2022-03-02igfx: maintain single/double-channel LVDS mode from BIOSMichael Forney
2022-03-02igfx: fix FDI link training on ironlakeMichael Forney
Ironlake uses bits 29:28 in the RX control register to select the training pattern.
2022-02-28aux/vga: return modes according to EDID timing priority orderMichael Forney
EDID 1.3 section 5 gives a table describing the priority order of timing information. Use this ordering when constructing the EDID mode list. Since aux/vga selects the first mode in the modelist that matches the given size, it will now select the mode of that size with the highest preference. Or, if you set vgasize=auto (or some other string without an 'x'), aux/vga will select the Preferred Detailed Timing. This should make it unnecessary to modify vgadb in many cases.
2021-11-26aux/vga: use vlong for pci bar sizecinap_lenrek
2021-11-12igfx: add x1 carbon 3rd gen (broadwell)Kyle Milz
2021-08-31vga: add eeepc1005ha graphics (thanks Andrew Eggenberger)cinap_lenrek
> This patch enables use of the igfx controller rather than vesa on the > eeepc1005ha netbook. This means using the full screen resolution of > 1024x600. > *Andrew Eggenberger*
2021-07-31[PATCH] Support for igfx on Celeron(R) 2957U (thanks Lorenzo Bivens)cinap_lenrek
> After some tinkering I managed to get igfx working on this device. > hw cursor works. > The only caveat is that I can only get video over hdmi... > will revisit displayport later
2020-12-27aux/vga: remove panning, add screen tilting supportcinap_lenrek
2020-09-26aux/vga: eepc igfx support (thanks p.kosyh)Ori Bernstein
This patch to makes 1024x600x32 work. Without it only 800x600 is supported. To load this mode, run: aux/vga -m eeepc -l 1024x600x32
2020-06-06aux/vga: use 64-bit physical addresses for pci membarcinap_lenrek
2019-03-04igfx: add support for 915gmqwx
tested on a t43 with igfx and a 1600x1200 t43p screen what works: lvds, blanking what doesn't: hwgc (not visible), snarfing edid untested: vga based on realemu traces.
2018-03-14nvidia: add pci device id for GeForce 6200 AGB (thanks bitmapper)cinap_lenrek
2018-03-04igfx: add support for T510 (thanks mycroftiv)cinap_lenrek
2017-12-23devvga: removing #v/vgabios, use /dev/realmodemem insteadcinap_lenrek
2017-11-13igfx: allocate backing memory for framebuffer and hw cursor when not done by ↵cinap_lenrek
bios (from qu7uux) new approach to graphics memory management: the kernel driver never really cared about the size of stolen memory directly. that was only to figure out the maximum allocation to place the hardware cursor image somewhere at the end of the allocation done by bios. qu7uux's gm965 bios however wont steal enougth memory for his native resolution so we have todo it manually. the userspace igfx driver will figure out how much the bios allocated by looking at the gtt only. then extend the memory by creating a "fixed" physical segment. the kernel driver allocates the memory for the cursor image from normal kernel memory, and just maps it into the gtt at the end of the virtual kernel framebuffer aperture. thanks to qu7uux for the patch.
2017-08-23igfx: fix cdclk and dpll settings for dual channel lvds on sandybridgeqwx
2017-08-20igfx: fix sandybridge fdi link training bits and orderingqwx
- fix wrong bitfield for txctl (different between snb and ivb), and enable tx before rx - DPLL_CTL_x snb/ivb: don't touch reserved bits
2017-06-25aux/vga: simplify vesa by adding rgbmask2chan() functioncinap_lenrek
2017-05-22igfx: add support for haswell graphicsqwx
add support for edp, dp and hdmi on haswell and haswell ult. vga, dvi and specific configurations like ulx are unimplemented. remaining issue: edp link training always fails (time out).
2016-08-20vga/igfx: work in progress fdi link train for sandy bridge, properly ↵cinap_lenrek
calculate fdi and displayport lane count
2016-06-30vga/igfx: fix integer overflow in datam calculation (from qu7uux)cinap_lenrek
data[mn] and link[mn] are 24-bit values. in the expression 'm = (n * ((freq * bpp)/8)) / (lsclk * lanes)', uvlongs are used to prevent integer overflow, but since freq, bpp, lsclk and lanes are all ints, the cast to uvlong does not happen until it's too late, getting a wrong value. instead, use u32int for m and n, and use casts where necessary. example of bad calculation: freq = 141400000 lsclk = 270000000 lanes = 2 bpp = 18 → 0x7f3ee1ca6 (correct value: 0x4b69d0)
2015-09-14igfx: fix typos (thanks qwx)cinap_lenrek
2015-08-03aux/vga: dont rely on atoi() being able to parse hexcinap_lenrek
2015-07-31aux/vga: sandybridge support for igfx (unfinished)cinap_lenrek
as usual, the dude with the hardware vanished so i cannot develop this further. setting mode worked the last time but only when using vesa before, so some bits are still missing. commiting this as it is so i dont have to start from scratch once we have hardware again.
2015-06-13aux/vga: == is not strncmpftrvxmtrx
2015-06-08aux/vga: disable nvidiascale() as it broke modeset on kenjis cardcinap_lenrek
this code needs revision, need a list of cards where this actually works.
2015-05-19aux/vga: dont use /proc/$pid/mem to access vga bioscinap_lenrek
using /proc/$pid/mem to access vga bios is not portable and crashes sgi machines when aux/vga is run. instead, try /dev/realmodemem first (provided by realemu), then #v/vgabios.
2015-02-26aux/vga: dont error when vesa setscale fails after modeset (thanks rx9p for ↵cinap_lenrek
reporting)
2015-02-09igfx: displayport support for ivy bridgecinap_lenrek
2015-02-07vga/igfx: add 0x2a02 for GM965/GL960/X3100; comment vid/did with name of chipsetstanley lieber
2015-02-05aux/vga: remove vbs/vbe from mode, use shs/ehs when sync is ment, prefer ↵cinap_lenrek
detailed timing in edid vbs/vbe members in Mode was only used in the vesadb and cannot be changed from vgadb. use shs/ehs in drivers when refering to the horizontal sync pulse. clarify the matter in a comment. link detailed timing modes at the head of the edid modelist. these are the modes we'r interested in, not the ones from vesadb.
2015-02-02aux/vga: fix mistale :-)cinap_lenrek
2015-02-02aux/vga: use optional edid information to determine mode when vgadb failscinap_lenrek
igfx and vesa can determine monitor timing information from ddc and store the edid info for connected monitors in vga->edid[]. when monitor type cannot be found in vgadb, we consult the edid information and make a mode based on the edid info. this avoids having to maintain a vgadb entry for each monitor. monitor can be set to "[width]x[height]@[freq]Hz" for a specific edid setting. when not found, a mode is searched based on the size. so the following should work: aux/vga -m 1366x768@60Hz -l 1366x768x32 aux/vga -m auto -l 1366x768x32
2015-02-01aux/vga: cleanup vesa codecinap_lenrek
dbvesamode() modified the passed in size string in the process of option parsing. this is a no-go because the string might be constant in the read only section. provide cracksize() function for the parsing and make a static copy. do the vendor specific monitor detection in vbesnarf() instead of vbecheck(). vbecheck()'s purpose is to check if vesa bios service is avialable, not snarf graphics card state. nvidiascale() was a no-op because it missed the vbecall() at the end of the function. this means it was never tested so i add the missing vbecall(), but disable nvidiascale for now until someone tests this. keep fancy stuff out of the Vbe structure. it is just there for making bios calls, not keep state about the graphics card.
2015-01-17igfx: fix wrong cursor position register addresscinap_lenrek
2015-01-16igfx: determine amount of preallocated stolen graphics memory for hw cursorcinap_lenrek
allocate the hardware cursor plane at the end of preallocated stolen graphics memory.
2015-01-16igfx: support for X60t with 1400x1050 panelcinap_lenrek
program secret plane size and position registers described as "reserved" in g45_vol_3_register_0_0.pdf that was found by inspecting vesa bios port traces. also, we have to set 18:19 (Cursor/Dispaly/Overlay Planes Off) in PIPExCONF while programming the planes on this card. this is what vesa bios does on modeset.
2015-01-13igfx: cursor/plane pipe assign is G45 only, add magic dsp a toggle from ↵cinap_lenrek
enable sequence
2015-01-12igfx: set the display/overlay/cursor plane override disbale bits for G45 ↵cinap_lenrek
(like bios)
2015-01-12igfx: fix typo, initialize more lvds bits for G45, T60 testingcinap_lenrek
2015-01-12igfx: reverting previous change, pci id is for the second graphics ↵cinap_lenrek
controller pci device
2015-01-12igfx: support for X200 (thanks bigato)cinap_lenrek
2015-01-12igfx: properly turn vga monitor offcinap_lenrek
2015-01-12igfx: aaand vga support for x200s :-)cinap_lenrek
2015-01-12igfx: vga support on x230, fix fdi link setup, LG Flatron L1730P vgadb entrycinap_lenrek